? semiconductor components industries, llc, 2011 october, 2011 ? rev. 7 1 publication order number: ntd4815n/d ntd4815n, NVD4815N power mosfet 30 v, 35 a, single n ? channel, dpak/ipak features ? low r ds(on) to minimize conduction losses ? low capacitance to minimize driver losses ? optimized gate charge to minimize switching losses ? aec ? q101 qualified and ppap capable ? NVD4815N ? these devices are pb ? free and are rohs compliant applications ? cpu power delivery ? dc ? dc converters ? high side switching maximum ratings (t j = 25 c unless otherwise stated) parameter symbol value unit drain ? to ? source voltage v dss 30 v gate ? to ? source voltage v gs 20 v continuous drain current r ja (note 1) steady state t a = 25 c i d 8.5 a t a = 85 c 6.5 power dissipation r ja (note 1) t a = 25 c p d 1.92 w continuous drain current r ja (note 2) t a = 25 c id 6.9 a t a = 85 c 5.3 power dissipation r ja (note 2) t a = 25 c p d 1.26 w continuous drain current r jc (note 1) t c = 25 c i d 35 a t c = 85 c 27 power dissipation r jc (note 1) t c = 25 c p d 32.6 w pulsed drain current t p =10 s t a = 25 c i dm 87 a current limited by package t a = 25 c i dmaxpkg 35 a operating junction and storage temperature t j , t stg ? 55 to +175 c source current (body diode) i s 27 a drain to source dv/dt dv/dt 6 v/ns single pulse drain ? to ? source avalanche energy (v dd = 24 v, v gs = 10 v, i l = 11 a pk , l = 1.0 mh, r g = 25 eas 60.5 mj lead temperature for soldering purposes (1/8? from case for 10 s) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. marking diagrams & pin assignments http://onsemi.com v (br)dss r ds(on) max i d max 30 v 15 m @ 10 v 35 a 25 m @ 4.5 v g s n ? channel mosfet d see detailed ordering and shipping information in the package dimensions section on p age 6 of this data sheet. ordering information yww 4815ng 1 gate 2 drain 3 source 4 drain 4 drain 2 drain 1 gate 3 source yww 4815ng y = year ww = work week 4815n = device code g = pb ? free package case 369aa dpak (bent lead) style 2 1 2 3 4 1 2 3 4 case 369ac 3 ipak (straight lead)
ntd4815n, NVD4815N http://onsemi.com 2 thermal resistance maximum ratings parameter symbol value unit junction ? to ? case (drain) r jc 4.6 c/w junction ? to ? tab (drain) r jc ? tab 3.5 junction ? to ? ambient ? steady state (note 1) r ja 78 junction ? to ? ambient ? steady state (note 2) r ja 119 1. surface ? mounted on fr4 board using 1 sq ? in pad, 1 oz cu. 2. surface ? mounted on fr4 board using the minimum recommended pad size. electrical characteristics (t j = 25 c unless otherwise specified) parameter symbol test condition min typ max unit off characteristics drain ? to ? source breakdown voltage v (br)dss v gs = 0 v, i d = 250 a 30 v drain ? to ? source breakdown voltage temperature coefficient v (br)dss / t j 25 mv/ c zero gate voltage drain current i dss v gs = 0 v, v ds = 24 v t j = 25 c 1 a t j = 125 c 10 gate ? to ? source leakage current i gss v ds = 0 v, v gs = 20 v 100 na on characteristics (note 3) gate threshold voltage v gs(th) v gs = v ds , i d = 250 a 1.5 2.5 v negative threshold temperature coefficient v gs(th) /t j 5.6 mv/ c drain ? to ? source on resistance r ds(on) v gs = 10 v to 11.5 v i d = 30 a 12 15 m i d = 15 a 11.5 v gs = 4.5 v i d = 30 a 21 25 i d = 15 a 18.3 forward transconductance g fs v ds = 15 v, i d = 10 a 6.0 s charges and capacitances input capacitance c iss v gs = 0 v, f = 1.0 mhz, v ds = 12 v 770 pf output capacitance c oss 181 reverse transfer capacitance c rss 108 total gate charge q g(tot) v gs = 4.5 v, v ds = 15 v; i d = 30 a 6.0 6.6 nc threshold gate charge q g(th) 0.9 gate ? to ? source charge q gs 2.5 gate ? to ? drain charge q gd 3.1 total gate charge q g(tot) v gs = 11.5 v, v ds = 15 v; i d = 30 a 14.1 nc switching characteristics (note 4) turn ? on delay time t d(on) v gs = 4.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 10.5 ns rise time t r 21.4 turn ? off delay time t d(off) 11.4 fall time t f 3.5 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd4815n, NVD4815N http://onsemi.com 3 electrical characteristics (t j = 25 c unless otherwise specified) parameter unit max typ min test condition symbol switching characteristics (note 4) turn ? on delay time t d(on) v gs = 11.5 v, v ds = 15 v, i d = 15 a, r g = 3.0 6.3 ns rise time t r 17.6 turn ? off delay time t d(off) 18.4 fall time t f 2.3 drain ? source diode characteristics forward diode voltage v sd v gs = 0 v, i s = 30 a t j = 25 c 1.0 1.2 v t j = 125 c 0.92 reverse recovery time t rr v gs = 0 v, dis/dt = 100 a/ s, i s = 30 a 15.3 ns charge time t a 8.7 discharge time t b 6.6 reverse recovery charge q rr 5.5 nc package parasitic values source inductance l s t a = 25 c 2.49 nh drain inductance, dpak l d 0.0164 drain inductance, ipak l d 1.88 gate inductance l g 3.46 gate resistance r g 2.6 3. pulse test: pulse width 300 s, duty cycle 2%. 4. switching characteristics are independent of operating junction temperatures.
ntd4815n, NVD4815N http://onsemi.com 4 typical performance curves 3.2 v 4 v 5.5 v to 10 v 5 0.020 15 0.005 0 30 1.5 1.0 0.5 10,000 100,000 0 30 2 1 v ds , drain ? to ? source voltage (volts) i d , drain current (amps) 0 v gs , gate ? to ? source voltage (volts) figure 1. on ? region characteristics figure 2. transfer characteristics i d , drain current (amps) 24 0.020 0.010 0 5 figure 3. on ? resistance vs. gate ? to ? source voltage v gs , gate ? to ? source voltage (volts) figure 4. on ? resistance vs. drain current and gate voltage i d , drain current (amps) r ds(on) , drain ? to ? source resistance ( ) r ds(on) , drain ? to ? source resistance ( ) figure 5. on ? resistance variation with temperature t j , junction temperature ( c) figure 6. drain ? to ? source leakage current vs. drain voltage v ds , drain ? to ? source voltage (volts) r ds(on) , drain ? to ? source resistance (normalized) i dss , leakage (na) ? 50 50 25 0 ? 25 75 125 100 23 16 12 32 4 3 v ds 10 v t j = 25 c t j = ? 55 c t j = 125 c v gs = 4.5 v 175 v gs = 0 v i d = 30 a v gs = 10 v 50 t j = 175 c t j = 125 c 40 0 45 t j = 25 c 20 10 5 v 3 v 2.0 10 1000 4 1 0 612 0.030 20 0.010 25 4.5 v 3.4 v 3.6 v 3.8 v 40 10 20 60 30 20 80 10 50 i d = 30 a t j = 25 c 789 0.005 0.015 0.025 v gs = 11.5 v 150 100 t j = 25 c 0.015 10 5 60 70 6789 31011 0.030 0.025 82428
ntd4815n, NVD4815N http://onsemi.com 5 typical performance curves c rss 10 0 10 15 30 gate ? to ? source or drain ? to ? source voltage (volts) c, capacitance (pf) figure 7. capacitance variation 1000 0 v gs v ds 1400 55 v gs = 0 v v ds = 0 v t j = 25 c c iss c oss c rss c iss 1300 1500 figure 8. gate ? to ? source and drain ? to ? source voltage vs. total charge 0 2 0 q g , total gate charge (nc) 1 4 6 5 i d = 30 a t j = 25 c q 2 q 1 q t 7 0 0.4 v sd , source ? to ? drain voltage (volts) i s , source current (amps) figure 9. resistive switching time variation vs. gate resistance r g , gate resistance (ohms) 1 10 100 1000 1 t, time (ns) v gs = 0 v figure 10. diode forward voltage vs. current 100 0.6 0.7 1.1 5 10 15 t r t d(off) t d(on) t f 10 v dd = 15 v i d = 30 a v gs = 11.5 v 0.8 0.9 20 30 25 t j = 25 c figure 11. maximum rated forward biased safe operating area 0.1 1 100 v ds , drain ? to ? source voltage (volts) 0.1 1000 i d , drain current (amps) r ds(on) limit thermal limit package limit 10 10 v gs = 20 v single pulse t c = 25 c 1 ms 100 s 10 ms dc 10 s 20 6 1 100 0 25 t j , junction temperature ( c) i d = 11 a figure 12. maximum avalanche energy vs. starting junction temperature 50 75 175 10 30 40 100 125 50 70 eas, single pulse drain ? to ? source avalanche energy (mj) 150 500 20 25 1200 1100 900 800 700 600 100 400 300 200 0.5 1.0 60 v gs , gate ? to ? source voltage (volts) 2 0 8 4 6 v ds , drain ? to ? source voltage (volts) 3 5 10 16 12 14 v gs v ds 3 24 1
ntd4815n, NVD4815N http://onsemi.com 6 typical performance curves figure 13. avalanche characteristics 1000 1 100 pulse width ( s) 0.1 i d , drain current (amps) 10 10 125 c 1 100 100 c 25 c figure 14. thermal response r(t), effective transient thermal resistance (normalized) t, time ( s) 0.1 1.0 0.01 0.1 0.2 0.02 d = 0.5 0.05 0.01 single pulse r jc (t) = r(t) r jc d curves apply for power pulse train shown read time at t 1 t j(pk) ? t c = p (pk) r jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 1.0e+00 1.0e+01 1.0e-01 1.0e-02 1.0e-03 1.0e-04 1.0e-05 ordering information device package shipping ? ntd4815nt4g dpak (pb ? free) 2500 / tape & reel ntd4815n ? 35g ipak trimmed lead (3.5 0.15 mm) (pb ? free) 75 units / rail NVD4815Nt4g dpak (pb ? free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ntd4815n, NVD4815N http://onsemi.com 7 package dimensions dpak (single guage) case 369aa ? 01 issue b b d e b3 l3 l4 b2 e m 0.005 (0.13) c c2 a c c z dim min max min max millimeters inches d 0.235 0.245 5.97 6.22 e 0.250 0.265 6.35 6.73 a 0.086 0.094 2.18 2.38 b 0.025 0.035 0.63 0.89 c2 0.018 0.024 0.46 0.61 b2 0.030 0.045 0.76 1.14 c 0.018 0.024 0.46 0.61 e 0.090 bsc 2.29 bsc b3 0.180 0.215 4.57 5.46 l4 ??? 0.040 ??? 1.01 l 0.055 0.070 1.40 1.78 l3 0.035 0.050 0.89 1.27 z 0.155 ??? 3.93 ??? notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. thermal pad contour optional within di- mensions b3, l3 and z. 4. dimensions d and e do not include mold flash, protrusions, or burrs. mold flash, protrusions, or gate burrs shall not exceed 0.006 inches per side. 5. dimensions d and e are determined at the outermost extremes of the plastic body. 6. datums a and b are determined at datum plane h. 12 3 4 h 0.370 0.410 9.40 10.41 a1 0.000 0.005 0.00 0.13 l1 0.108 ref 2.74 ref l2 0.020 bsc 0.51 bsc a1 h detail a seating plane a b c l1 l h l2 gauge plane detail a rotated 90 cw style 2: pin 1. gate 2. drain 3. source 4. drain 5.80 0.228 2.58 0.102 1.60 0.063 6.20 0.244 3.00 0.118 6.17 0.243 mm inches scale 3:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ntd4815n, NVD4815N http://onsemi.com 8 package dimensions 3 ipak, straight lead case 369ac ? 01 issue o d a k b r v f g 3 pl e c j h dim min max min max millimeters inches a 0.235 0.245 5.97 6.22 b 0.250 0.265 6.35 6.73 c 0.086 0.094 2.19 2.38 d 0.027 0.035 0.69 0.88 e 0.018 0.023 0.46 0.58 f 0.037 0.043 0.94 1.09 g 0.090 bsc 2.29 bsc h 0.034 0.040 0.87 1.01 j 0.018 0.023 0.46 0.58 k 0.134 0.142 3.40 3.60 r 0.180 0.215 4.57 5.46 v 0.035 0.050 0.89 1.27 w 0.000 0.010 0.000 0.25 notes: 1.. dimensioning and tolerancing per ansi y14.5m, 1982. 2.. controlling dimension: inch. 3. seating plane is on top of dambar position. 4. dimension a does not include dambar position or mold gate. w seating plane 0.13 (0.005) w on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ntd4815n/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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